1. Talaska T., (2017), Implementation of fuzzy logic operators as digital asynchronous circuits in CMOS technology. Proc. 30 th Conf. Microelectron.

2. Wilamowski B. M., (1998), Analog VLSI hardware for fuzzy systems, Proceedings of the 24 th Annual Conference of the IEEE Industrial Electronics Society, IECON '98.

3. Azizian S., Aziz Aghchegala V., Azizian S., Sefidgar Dilmaghani M., (2019), CMOS bulk-controlled fully programmable neuron for artificial neural networks. IETE J. Res. 65: 320-328.

4. Azizian S., Fathi K., Mashoufi B., Derogarian F., (2011), Implementation of a programmable neuron in 0.35 μm CMOS process for multi-layer ANN applications. Eurocon-Int. Conf. Comp. Tool. 1-4.

5. Zavala A. H., Nieto O. C., (2012), Fuzzy hardware: A retrospective and analysis. IEEE Transact. Fuzzy Sys. 20: 623-635.

6. Yaghmourali Y. V., Fathi A., Hassanzadazar M., Khoei A., Hadidi K., (2018), A low-power, fully programmable membership function generator using both transconductance and current modes. Fuzzy Sets and Systems. 337: 128-142.

7. Gabrielli A., Gandolfi E., Masetti M., Maloberti f., (1995), Design and preliminary results of high speed analog 1.0/spl mu/m CMOS MIN-MAX circuit for fuzzy architectures. Proceedings of the 38th Midwest Symposium on Circuits and Systems.

8. Aksin D. Y., (2002), A high-precision high-resolution WTA–MAX circuit of O (N) complexity. IEEE Transact. Circ. Systems—II: Analog. Digital Signal Process. 49: 48-53.

9. Madrenas J., Fernández d., Cosp J., (2010), A low-voltage current sorting circuit based on 4-T min-max CMOS switch. 17 th IEEE Int. Conf. Electron. Circuits, and Systems (ICECS).

10. Shayanfar R., Khoei A., Hadidi K., (2010), Multi-input voltage-mode min-max circuit. 18 th Iran. Conf. Elect. Eng. (ICEE).

11. Padash M., Khoei A., Hadidi K., Ghasemiyan H., (2011), A high precision high frequency VLSI multi-input min-max circuit based on WTA-LTA cells. Int. Conf. Elect. Dev. Sys. Applicat. (ICEDSA).

12. Moaiyeri M. M., Chavoshisani R., Jalali A., Navi K., Hashemipour O., (2012), High-performance mixed-mode universal min-max circuits for nanotechnology. Syst. Signal Proc. 31: 465–488.

13. Fathi A., Khoei A., Hadidi K., (2015), High speed min/max architecture based on a novel comparator in 0.18-μm CMOS process. Circuit. Syst. Comput. 24: 1550048.

14. Mane S. C., Hajare S. P., Dakhole P., (2017), Current mode quaternary logic circuit. Conf. Communic. Signal Processing.

15. Amirkhanzadeh R., Khoei A., Hadidi K., (2005), A mixed-signal current-mode fuzzy logic controller. AEU-Int. J. Electron. Commun. 59: 177–184.

16. Liu C., Cheng H., (2013), Carbon nanotubes: Controlled growth and application. Materials Today. 16: 19-28.

17. Avouris P., Afzali A., Appenzeller J., Chen J., Freitag M., Klinke C., Lin Y.-M., Tsang J. C., (2004), Carbon nanotube electronics and optoelectronics. Digest-IEEE Int. Elect. Dev. Meet. (IEDM). 525-529.

18. Franklin A. D., (2013), Electronics: The road to carbon nanotube transistors. 498: 443–444.

19. Rahnamaei A., Zare Fatin G., Eskandarian A., (2019), Design of a low power high speed 4-2 compressor using CNTFET 32 nm technology for parallel multipliers. Int. J. Nano Dimens. 10: 114-124.

20. Rahnamaei A., Zare Fatin G., Eskandarian A., (2019), High speed radix-4 booth scheme in CNTFET technology for high performance parallel multipliers. J. Nano Dimens. 10: 281-290.

21. Seyed Aalinejad S. M., (2019), Implementation of a programmable neuron in CNTFET technology for low-power neural networks. J. Nano Dimens. 11: 120-129.

22. Yousefi R., Saghafi K., Moravvej-Farshi M. K., (2010), Application of neural space mapping for modeling ballistic carbon nanotube transistors. J. Electric. Electron. Eng. 6: 70-76.

23. Abdollahzadeh Badelbo R., Farokhi F., Kashaniniya A., (2013), Efficient parameters selection for CNTFET modelling using artificial neural networks. J. Smart Elect. Eng. 2: 217-222.

24. Zhang J., Chang Sh., Wang H., He J., Huang O., (2014), Artificial neural network based CNTFETs modeling. Mechanic. Mater. 667: 390-395.

25. Friesz A. K., Parker A. C., Zhou Ch., Philip Wong H.-S., Deng J., (2007), A biomimetic carbon nanotube synapse circuit, biomedical engineering society (BMES), Annual Fall Meeting.

26. Joshi J., Zhang J., Wang Ch., Hsu Ch.-Ch., Parker A. C., Zhou Ch., Ravishankar U., (2011), A biomimetic fabricated carbon nanotube synapse for prosthetic applications. IEEE/NIH Life Science Systems and Applications Workshop (LiSSA).

27. Najari M., El-Grour T., Jelliti S., Mousa Hakami O., (2016), Simulation of a spiking neuron circuit using carbon nanotube transistors. Proceedings of The Fifth Saudi International Meeting on Frontiers of Physics (SIMFP2016).

28. Moaiyeri M. H., Chavoshisani R., Jalali A., (2012), High-performance mixed-mode universal min-max circuits for nanotechnology. Syst. Signal Proc. 31: 465–488.

29. Zaki F., Mustajab P., (2019), Voltage mode CNFET based fuzzy min-max circuits. Conf. Elect. Electron. Comput. Eng. (UPCON).

30. Pendashteh Y., Hosseini S. A., (2021), Novel low-complexity and energy-efficient fuzzy min and max circuits in nanoelectronics. AEU- Int. J. Elect. Communic. 138: 153858.

31. Ali B., Rahman M., Rahman H. R., (2012), Design and optimization of nanometric reversible 4 bit numerical comparator. IEEE/OSAIIAPR Int. Conf. Inform. Elect. & Vision.

32. Dibal P. Y., (2013), Design of A 4-bit magnitude comparator using simulink, arid zone. Eng. Technol. Envir. 9: 9-16.

33. Prajapat G., Joshi A., Jain A., Verma K., Jaiswal S. K., (2013), Design of low power and high speed 4-bit comparator using transmission gate. Conf. Machine Intellig. Res. Adv.

34. Sharma A., Sharma P., (2014), Area and power efficient 4–bit comparator design by using 1-bit full adder module. Int. Conf. Parallel, Distrib. Grid Computing.

35. Fathi A., Azizian S., Sharifan N., (2017), Sensors and amplifiers: Sensor output signal amplification systems. In Handbook of Res. Nanoelectron. Sensor Model. Applic. 423-504, IGI Global.

36. Javey A., Guo J., Farmer D. B., Wang Q., Wang D., Gordon R. G., Lundstrom M., Dai H., (2004), Carbon nanotube field-effect transistors with integrated ohmic contacts and high-k gate dielectrics. Nano Lett. 4: 447-450.

37. Tijjani A., Galadanci G. S. M., Babaji G., (2020), Drain current characteristics of carbon-nanotube FET (CNTFET) with SiO2, ZrO2 and HfO2 as dielectric materials using FETToy code. NIPES Sci. Technol. Res. 2: 212-227.