[1] Safaei Mehrabani Y., Eshghi M., (2016), Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology. IEEE Transact. Very Large Scale Integ. (VLSI) Systems. 24: 3268–3281.

[2] Niedzicka A., (2002), Computation-intensive image processing algorithm parallelization on multiple hardware architectures, Proceedings. Int. Conf. Parallel Comp. Elect. Eng., Warsaw, Poland. 446–448.

[3] Schlachter J., Camus V., Palem K. V., Enz C., (2017), Design and applications of approximate circuits by gate-level pruning. IEEE Transact. Very Large Scale Integ. (VLSI) Systems. 25: 1694–1702.

[4] Mohammadi Ghanatghestani M., Ghavami B., Pedram H., (2018), A ternary full adder cell based on carbon nanotube FET for high-speed arithmetic units. J. Nanoelec. Opt. Am. Sci. Pub. 13: 368-377.

[5] Safaei Mehrabani Y., Eshghi M., (2015), High-speed, high-frequency and low-PDP, CNFET full adder cells. J. Circ. Sys. Computers (JCSC). 24: 1550130-1550144.

[6] Murray K. E., (2020), Optimizing FPGA logic block architectures for arithmetic. IEEE Transact. Very Large Scale Integ. (VLSI) Systems. 28: 1378–1391.

[7] Rahnamaei A., Zare Fatin Gh., Eskandarian A., (2019), Design of a low power high speed 4-2 compressor using CNTFET 32 nm technology for parallel multipliers. Int. J. Nano Dimens. 10: 114-124.

[8] Cho G., Kim Y.-B., Lombardi F., Choi M., (2009), Performance evaluation of CNFET-based logic gates. IEEE Instrum. Measur. Technol. Conf. Singapore. 909–912.

[9] Sinha S. K., Kumar K., Chaudhury S., (2013), CNTFET: The emerging post-CMOS device. Int. Conf. Signal Process. Communic. (ICSC). Noida. 372–374.

[10] Sadeghi B., Vahdati R. A. R., (2012), Comparison and SEM-characterization of novel solvents of DNA/carbon nanotube. Appl. Surf. Sci. 258: 3086-3088.

[11] Safaei Mehrabani Y., Eshghi M., (2015), A Symmetric, multi-threshold, high-speed and efficient-energy 1-bit full adder cell design using CNFET technology. Circ. Sys. Sig. Process. 34: 739–759.

[12] Lin S., Kim Y. B.,  Lombardi F., (2011), CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10: 217–225.

[13] Tans S. J., Verschueren A. R. M., Dekker C., (1998), Room-temperature transistor based on a single carbon nanotube. Nature. 393: 49–52.

[14] Shahi A. A. M., Zarkesh-Ha P., Elahi M., (2012), Comparison of variations in MOSFET versus CNFET in gigascale integrated systems. IEEE 13th Int. Symp. Quality Elect. Des. 378–383.

[15] Mohammadi Ghanatghestani M., Pedram H., Ghavami B., (2015), Design of a low-standby power and high-speed ternary memory cell based on carbon nanotube FET. J. Comput. Theoret. Nanosci. Am. Sci. Pub. 12: 5457-5462.

 [16] O'Connor I., Liu J., Gaffiot F., Prégaldiny F., Lallement C., Maneux C., Goguet J., (2007), CNTFET modeling and reconfigurable logic-circuit design. IEEE Transact. Circ. Sys. I: Reg. Papers. 54: 2365–2379.

[17] Xu Q., Mytkowicz T., Kim N. S., (2015), Approximate computing: A survey. IEEE Design & Test. 33: 8–22.

[18] Jothin R., Mohamed M. P., Vasanthanayaki C., (2020), High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications. Microproc. Microsys. 78: 103237-103241.

[19] Rostami D., Eshghi M., Safaei Mehrabani Y., (2021), Low-power and high-speed approximate 4 : 2 compressors for image multiplication applications in CNFETs. Int. J. Elec. 108: 1288-1308.

[20] Liang J., Han J., Lombardi F., (2012), New metrics for the reliability of approximate and probabilistic adders. IEEE Transact. Comput. 62: 1760–1771.

[21] Liu W., Zhang T., McLarnon E., O'Neill M., Montuschi P., Lombardi F., (2019), Design and analysis of majority logic based approximate adders and multipliers. IEEE Transact. Emerg. Top. Computing (TETC).10: 83-87.

[22] Yang Z., Han J., Lombardi F., (2015), Transmission gate-based approximate adders for inexact computing. IEEE/ACM Int. Symp. Nanosc. Archit. (NANOARCH´15), Boston. 145–150.

[23] Almurib H. A. F., Kumar T. N., Lombardi F., (2016), Inexact designs for approximate low power addition by cell replacement. IEEE Design, Automat. Test Europe Conf. Exhib. (DATE), Dresden. 660–665.

[24] Safaei Mehrabani Y., Faghih Mirzaee R., Zareei Z., Daryabari S. M., (2017), A novel high-speed, low-power CNTFET-based inexact full adder cell for image processing application of motion detector. J. Circ. Sys. Comput. (JCSC). 26: 1750082-1–1750082-15.

[25] Goyal C., Ubhi J. S., Raj B., (2019), A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications. Int. J. Circ. Theory and Applicat. 47: 1446–1458.

[26] Ataie R., Emrani Zarandi A. A., Mehrabani Safaei Y., (2019), An efficient inexact full adder cell design in CNFET technology with high-PSNR for image processing. Int. J. Elect. 106: 928–944.

[27] Mirzaei M., Mohammadi S., (2020), Process variation-aware approximate full adders for imprecision-tolerant applications. Comput. Elect. Eng. 87: 106761-106765.

[28] Deng J., Philip Wong H-S., (2007), A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region. IEEE Transact. Elec. Dev. 54: 3186–3194.

[29] Deng J., Philip Wong H-S., (2007), A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking. IEEE Transact. Elect. Dev. 54: 3195–3205.

[30] Harris D., Sutherland I., (2003), Logical effort of carry propagate adders. The thrity-seventh asilomar conference on signals, systems & computers, 2003, Pacific Grove, CA, USA. 873–878.

[31] Govindarajulu S., Prasad T. J., (2008), Considerations of performance factors in CMOS designs. Int. Conf. Elect. Des., Penang. 1–6.

[32] Cho G., Kim Y., Lombardi F., (2009), Assessment of CNTFET based circuit performance and robustness to PVT variations. 52 nd IEEE Int. Midwest Symp. Circ. Sys. Cancun. 1106–1109.

[33] El Shabrawy K., Maharatna K., Bagnall D., Al-Hashimi B. M., (2010), Modeling SWCNT bandgap and effective mass variation using a monte carlo approach. IEEE Transact. Nanotechnol. 9: 184–193.

[34] Dosselmann R., Dong Yang X., (2005), Existing and emerging image quality metrics. Canad. Conf. Elect. Comput. Eng. Saskatoon, Sask. 1906-1913.

[35] Tahaei S. H., Ghoreishi S. S., Yousefi R., Aderang H., (2019), A computational study of a carbon nanotube junctionless tunneling field-effect transistor (CNT-JLTFET) based on the charge plasma concept. Superlatt. Microstruct. 125: 168–176.

[36] Tahaei S. H., Ghoreishi S. S., Yousefi R., Aderang H., (2019), A computational study of a heterostructure tunneling carbon nanotube field-effect transistor. J. Elect. Mater. 48: 7048–7054.