Julian, L.: Multiplications and Convolutions in L Schwartz’ Spaces of Test Functions and Distributions and their Continuity. Analysis 33, 319–332 (2013). https://doi.org/10.1524/anly.2013.1200

Article  MathSciNet  MATH  Google Scholar 

Liu, Z., Tian, X., Chen, L.: Efficient vectorization method of triangular matrix multiplication supporting in- place calculation. J. Natl. Univ. Def. Technol. 36, 7–11 (2014). https://doi.org/10.11887/j.cn.201406002

Article  MATH  Google Scholar 

Zhu, W.W., Zhang, L., Lu, Y.Y., Zhou, P., Yang, L.: Design and experimental verification for optical module of optical vector-matrix multiplier. Appl. Opt. 52, 4412–4418 (2013)

Article  ADS  MATH  Google Scholar 

Nitta, K., Matoba, O., Yoshimura, T.: Parallel processing for multiplication modulo by means of phase modulation. Appl. Opt. 47, 611–616 (2008)

Article  ADS  MATH  Google Scholar 

Lin, G.R., Wu, J.R.: Tenth-order rational-harmonic frequency multiplication and detuning of optical pulse injection-locked erbium doped fiber laser. Appl. Opt. 44, 2416–2420 (2005)

Article  ADS  MATH  Google Scholar 

Waser, S.: High-speed monolithic multipliers for real-time digital signal processing[J]. Computer 11(10), 19–29 (1978)

Article  MATH  Google Scholar 

Ma, G.K., Taylor, F.J.: Multiplier policies for digital signal processing. IEEE ASSP Mag. (1990). https://doi.org/10.1109/53.45968

Article  MATH  Google Scholar 

Kumar, D., Lall, G.C.: Simulation and synthesis of 32-bit multiplier using configurable devices. Int J Adv Eng Technol 5(2), 1 (2013)

Article  MATH  Google Scholar 

Liang, G., Zhimin, T.: A pipelined multiplier supporting unsigned numbers [J]. Microelectron. Comp. 19(10), 17–19 (2002). https://doi.org/10.19304/j.cnki.issn1000-7180.2002.10.006

Article  MATH  Google Scholar 

Wu, J.P., Wang, Z.H., Li, X.M.: Improve the Performance of Parallel Matrix Multiplication on Clustered SMP Systems Through Hybrid Programming[J]. J Nat Univ Defen Technol (2006). https://doi.org/10.3969/j.issn.1001-2486.2006.04.015

Article  MATH  Google Scholar 

Algirdas, A.: Signed-Digit Numbe Representations for Fast Parallel Arithmetic[J]. Electron Comp Ire Trans. 10(3), 389–400 (2000). https://doi.org/10.1109/TEC.1961.5219227

Article  MATH  Google Scholar 

Jin, Y., He, H., Yangtian, L.: Ternary optical computer principle[J]. Sci. China Series F (2003). https://doi.org/10.1360/03yf9012

Article  MATH  Google Scholar 

Yi, J., Huacan, H.E., Lirong, A.: Lane of parallel through carry in ternary optical adder[J]. Sci China (Series F) 48(1), 10 (2005). https://doi.org/10.1360/03yf0445

Article  MathSciNet  MATH  Google Scholar 

Song, K., Yan, L.P.: Design and implementation of the one-step MSD adder of optical computer. Appl. Opt. 51, 917–926 (2012)

Article  ADS  MATH  Google Scholar 

Kai, S., Liping, Y.: The symmetric MSD encoder for one-step adder of ternary optical computer[J]. Opt Commun 372, 221–228 (2016). https://doi.org/10.1016/j.optcom.2016.04.034

Article  ADS  MATH  Google Scholar 

Kai, S., Liping, Y.: Reconfigurable ternary optical processor based on row operation unit[J]. Opt Commun 350, 6–12 (2015). https://doi.org/10.1016/j.optcom.2015.03.080

Article  ADS  MATH  Google Scholar 

Wang, H., Song, K.: Simulative method for the optical processor reconfiguration on a dynamically reconfigurable optical platform[J]. Appl Opt 51(2), 167 (2012). https://doi.org/10.1364/AO.51.000167

Article  ADS  MATH  Google Scholar 

Qun, X., Xianchao, W., Chao, X.: Design and implementation of the modified signed digit multiplication routine on a ternary optical computer[J]. Appl Opt 56(16), 4661 (2017). https://doi.org/10.1364/AO.56.004661

Article  MATH  Google Scholar 

Jin, Y., Zhang, Hong Hong, Zhang, Xun Lei, et al.: Theory and Structure of the SD16 Ternary Logic Optical Calculator. Acta Electron Sinica. 51(5), 1154–1162 (2023). https://doi.org/10.12263/DZXB.20221096

Article  MATH  Google Scholar 

Drake, B.L., et al.: Photonic Computing Using The Modified Signed-Digit Number Representation[J]. Opt Eng 25(1), 38–43 (1986). https://doi.org/10.1117/12.7973778

Article  MathSciNet  MATH  Google Scholar 

Peng, J., Shen, R., Jin, Y., et al.: Design and Implementation of Modified Signed-Digit Adder[J]. IEEE Trans Comp 63(5), 1134–1143 (2014). https://doi.org/10.1109/TC.2012.285

Article  MathSciNet  MATH  Google Scholar 

Rebacz, J., Oruklu, E., Saniie, J.: Fast Signed-Digit Multi-operand Decimal Adders[J]. Circuit Syst 2(3), 225–236 (2011). https://doi.org/10.4236/cs.2011.23032

Article  Google Scholar 

Shen, Y., Pan, L., Jin, Y., et al.: One-step binary MSD adder for ternary optical computer[J]. Sci Sinica (Informationis) 42(7), 869 (2012). https://doi.org/10.1360/112012-63

Article  MATH  Google Scholar 

Yi, J., Huacan, H., Lü, Y.: Ternary Optical Computer Architecture[J]. Phys Scripta 118(T118), 98 (2005). https://doi.org/10.1238/Physica.Topical.118a00098

Article  MATH  Google Scholar 

Hu, X.J., Yi, J., Ouyang, S.: A 40-Bit Multiplication Routine of Ternary Optical Computer[J]. J Shan Univ (2014). https://doi.org/10.3969/j.issn.1007-2861.2014.01.003

Article  MATH  Google Scholar 

Wang, X., Peng, J., Jin, Y., et al.: Vector-Matrix Multiplication Based on a Ternary Optical Computer[J]. Sprin (2010). https://doi.org/10.1007/978-3-642-11842-5_59

Article  MATH  Google Scholar 

Bell, D.S., Greenes, R.A.: Evaluation of UltraSTAR: performance of a collaborative structured data entry system[J]. PubMed (1994). https://doi.org/10.1080/00949659408811593

Article  MATH  Google Scholar 

Yan, J.Y., Jin, Y., Zuo, K.Z.: Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer[J]. Sci China (Series F) 51(10), 12 (2008). https://doi.org/10.1007/s11432-008-0140-z

Article  MathSciNet  MATH  Google Scholar