Low power consumption is always the goal for the research and development of semiconductor digital transistors. Limited by the Fermi–Dirac distribution and the drift-diffusion transport of carriers, the conventional field-effect transistors (FETs) cannot achieve subthreshold swings (SS) below 60 mV/dec at 300 K. A few technologies have been proposed to break this constraint, such as ferroelectric gate dielectric featuring negative capacitance characteristics,1–31. A. Rusu, G. A. Salvatore, D. Jiménez, and A. M. Ionescu, in 2010 International Electron Devices Meeting ( IEEE, 2010), pp. 16.3.1–16.3.4.2. A. Saeidi, T. Rosca, E. Memisevic, I. Stolichnov, M. Cavalieri, L.-E. Wernersson, and A. M. Ionescu, Nano Lett. 20, 3255 (2020). https://doi.org/10.1021/acs.nanolett.9b053563. Q. Xu, X. Liu, B. Wan, Z. Yang, F. Li, J. Lu, G. Hu, C. Pan, and Z. L. Wang, ACS Nano 12, 9608 (2018). https://doi.org/10.1021/acsnano.8b05604 tunneling transistors,44. K. S. Singh, S. Kumar, K. Nigam, and V. A. Tikkiwal, in 2019 International Conference on Signal Processing and Communication (ICSC) ( IEEE, 2019), pp. 286–291. and impact-ionization transistors;55. D. Han, G. Bonomo, D. C. Ruiz, A. M. Arabhavi, O. J. S. Ostinelli, and C. R. Bolognesi, IEEE Trans. Electron Devices 69, 3549 (2022). https://doi.org/10.1109/TED.2022.3171736 however, there is still not a satisfactory solution until today to realize a transistor with a combination of high on-current, deep SS, and fast switching time. It is highly desirable to explore more possibilities on the materials, structures, and fabrication techniques to realize a transistor with deep sub-60 mV/dec SS and other excellent performance.GaN electronic devices have been regarded as one of the most promising candidates for the energy-efficient communication and power systems applications. During recent years, GaN-based devices have also been paid attention to for realizing deep SS for logic applications.6–106. Q. Zhou, S. Huang, H. Chen, C. Zhou, Z. Feng, S. Cai, and K. J. Chen, in 2011 International Electron Devices Meeting ( IEEE, Washington, D.C., 2011), pp. 33.4.1–33.4.4.7. H. W. Then, S. Dasgupta, M. Radosavljevic, L. Chow, B. Chu-Kung, G. Dewey, S. Gardner, X. Gao, J. Kavalieros, N. Mukherjee, M. Metz, M. Oliver, R. Pillarisetty, V. Rao, S. H. Sung, G. Yang, and R. Chau, in 2013 IEEE International Electron Devices Meeting ( IEEE, Washington, D.C., 2013), pp. 28.3.1–28.3.4.8. P. Cui, G. Lin, J. Zhang, and Y. Zeng, IEEE Electron Device Lett. 41, 1185 (2020). https://doi.org/10.1109/LED.2020.30033379. B. Song, M. Zhu, Z. Hu, M. Qi, X. Yan, Y. Cao, E. Kohn, D. Jena, and H. G. Xing, in 2014 Silicon Nanoelectronics Workshop (SNW) ( IEEE, Honolulu, HI, 2014), pp. 1–2.10. Q. Dai, D.-H. Son, Y.-J. Yoon, J.-G. Kim, X. Jin, I.-M. Kang, D.-H. Kim, Y. Xu, S. Cristoloveanu, and J.-H. Lee, IEEE Trans. Electron Devices 66, 1699 (2019). https://doi.org/10.1109/TED.2019.2900995 Zhou et al. reported sub-60 mV/dec SS in an Al2O3/InAlN/GaN metal–insulator–semiconductor high electron mobility transistor (MISHEMT) with Schottky source/drain contacts.66. Q. Zhou, S. Huang, H. Chen, C. Zhou, Z. Feng, S. Cai, and K. J. Chen, in 2011 International Electron Devices Meeting ( IEEE, Washington, D.C., 2011), pp. 33.4.1–33.4.4. Then et al. reported a “negative” capacitance phenomenon and a SS steeper than 40 mV/dec in an Al2O3/InAlN/GaN MISHEMT.77. H. W. Then, S. Dasgupta, M. Radosavljevic, L. Chow, B. Chu-Kung, G. Dewey, S. Gardner, X. Gao, J. Kavalieros, N. Mukherjee, M. Metz, M. Oliver, R. Pillarisetty, V. Rao, S. H. Sung, G. Yang, and R. Chau, in 2013 IEEE International Electron Devices Meeting ( IEEE, Washington, D.C., 2013), pp. 28.3.1–28.3.4. Cui et al. reported a sub-60 mV/dec SS via hot electron transfer in a InAlN/GaN MISHEMT with a gate oxide insulator layer formed by oxygen plasma oxidation.88. P. Cui, G. Lin, J. Zhang, and Y. Zeng, IEEE Electron Device Lett. 41, 1185 (2020). https://doi.org/10.1109/LED.2020.3003337 Al0.26Ga0.74N/GaN MISHEMTs with ALD-SiN/Al2O3/SiN gate dielectric99. B. Song, M. Zhu, Z. Hu, M. Qi, X. Yan, Y. Cao, E. Kohn, D. Jena, and H. G. Xing, in 2014 Silicon Nanoelectronics Workshop (SNW) ( IEEE, Honolulu, HI, 2014), pp. 1–2. and AlGaN/GaN Fin-MISHEMTs have also been found to have sub-60 mV/dec SS characteristics.1010. Q. Dai, D.-H. Son, Y.-J. Yoon, J.-G. Kim, X. Jin, I.-M. Kang, D.-H. Kim, Y. Xu, S. Cristoloveanu, and J.-H. Lee, IEEE Trans. Electron Devices 66, 1699 (2019). https://doi.org/10.1109/TED.2019.2900995 However, all the above reported GaN HEMT devices exhibiting a single-direction gate bias sweep sub-60 mV/dec SS characteristics share a common feature using ex situ gate insulator dielectric.

In this work, we report in situ SiN/Al0.6Ga0.4N/GaN MISHEMTs on a Si substrate with deep sub-60 mV/dec SS over 3–4 orders of drain current (ID) swing during both forward and reverse gate bias sweeps. The intrinsic physical mechanisms of the deep sub-60 mV/dec SS independent of gate bias sweep direction were comprehensively studied.

The cross section schematic of the fabricated in situ SiN/Al0.6Ga0.4N/GaN MISHEMT on a Si substrate is depicted in Fig. 1(a). The epitaxial structure is composed of a 1.7-μm undoped GaN buffer layer, a 5-nm Al0.6Ga0.4N barrier layer, and an 8-nm in situ SiN layer. The room temperature Hall measurement of the as-grown heterostructure revealed a two-dimensional electron gas (2DEG) density of 2.2 × 1013 cm−2 and an electron mobility of 1190 cm2/V s at room temperature. The device fabrication started from the planar isolation formed by multi-energy argon ion implantation, followed by the deposition of patterned Ti/Al/Ni/Au (20/120/40/50 nm) stack metal on the in situ SiN surface, and alloyed at 850 °C for 30 s using a rapid thermal annealing (RTA) furnace in N2 atmosphere to form source and drain Ohmic contacts. The contact resistance RC was measured to be 0.17 Ω mm. The in situ grown SiN thin layer was contributed to the low RC.1111. H. Du, Z. Liu, L. Hao, W. Xing, W. Zhang, H. Zhou, J. Zhang, and Y. Hao, Appl. Phys. Lett. 121, 172102 (2022). https://doi.org/10.1063/5.0100329 Finally, the gate electrode was patterned using electron beam lithography followed by Ni/Au (30/100 nm) metal stack deposition and liftoff. The fabricated devices have a gate length LG of 75, 120, 200, and 350 nm. The source-to-drain distance LSD is 1.8 μm for all the devices. The electrical characterization was performed using a Keithley 4200 Semiconductor Parameter Analyzer System.DC output characteristics of the fabricated 75-nm gate device with dual sweeps of the drain bias VDS at different VGS biases is plotted in Fig. 1(b). A maximum ID of 2.1 A/mm was obtained at VGS = 1 V. The device exhibits a low on-resistance Ron of 1.3 Ω mm. The drain current when VDS was swept downward from 10 to 0 V is smaller than that when VDS was swept upward, due to the trapping effect and the self-heating effect. The obvious kinks in the output curves reveal the de-trapping of the electrons captured in the buffer traps under a certain electric field.1212. M. Wang and K. J. Chen, IEEE Electron Device Lett. 32, 482 (2011). https://doi.org/10.1109/LED.2011.2105460The DC transfer performance and the gate current IG in the 75-nm gate device at VDS = 10 V under forward/reverse VGS sweeps was plotted in Fig. 1(c). Despite the ultra-high 2DEG density at the Al0.6Ga0.4N/GaN heterostructure, the 75-nm long gate can effectively pinch off the channel in the device. The threshold voltage has a slight negative shift under reverse VGS sweep compared to that under forward seep. SS values of 22 and 29 mV/dec for the forward/reverse sweeps, respectively, were achieved over a wide ID range up to 4 orders. There is an obvious negative differential resistance (NDR) phenomenon in the IG-VG curve, and it can be found that the gate biases at which the NDR phenomenon is observed are clearly associated with those where SS values are below 60 mV/dec.Figure 1(d) shows the measured SS values as a function of the drain bias VDS for devices with different gate lengths LG of 75, 120, 200, and 350 nm. The SS values were found to depend on the drain bias and the gate length. As for the device with 75 nm gate length, when VDS is lower than 8 V, the SS values are high and more than 60 mV/dec (∼75–80 mV/dec). When VDS is not lower than 8 V, the SS values drop to sub-60 mV/dec. There is not much difference between the measured SS values under VGS reverse or forward sweeps. In addition, the SS slightly increases when the gate length increases. All the devices with different gate length show the same trend, that is, when the VDS is small, the SS values are high and more than 60 mV/dec (∼65–85 mV/dec for Lg from 75 to 300 nm), while when VDS is beyond a certain value, the SS drops to sub-60 mV/dec. The VDS value at which the SS starts to be below 60 mV/dec is lager for the device with a longer gate, as summarized in Fig. 1(e), implying that the deep SS values measured in the devices are related to the electric field strength induced by VDS. When the gate length increases, the electric field peak at the depletion region under the gate is reduced, which makes the critical VDS at which the SS starts to drop to sub-60 mV/dec increase.The intrinsic mechanisms of the deep sub-60 mV/dec SS are believed to relate to the electron trapping and de-trapping at the in situ SiN/Al0.6Ga0.4N interface and in the buffer. A gate-to-drain C–V measurement was performed for the 75-nm gate device, and the measured results are shown in Fig. 1(f). The parasitic capacitance was not subtracted, and it is not larger than 0.8 μF/cm2 as seen from Fig. 1(f). An extremely high capacitance spike was found in the depletion region during both forward and reverse sweeps, which implies the existence of traps at the interface between the in situ SiN gate dielectric and the Al0.6Ga0.4N barrier layer.The physical process of the trapping and de-trapping during the device turn-on and pinch-off can be explained with Figs. 2(a)–2(d). At VGS = 0 V, part of the traps are unfilled and located at the SiN/Al0.6Ga0.4N interface and in the GaN buffer layer. When the device is biased at a negative voltage, the hot electrons induced by the strong electric field in the channel spill over the barrier and into the buffer, and then are trapped at the SiN/Al0.6Ga0.4N interface and in the buffer. In addition, the injected electrons from the gate electrode are also trapped at the SiN/Al0.6Ga0.4N interface. The trapped electrons cannot be released immediately, so they form negative charges located above and below the channel, which effectively accelerate the depletion of the electrons in the channel. Thus, a deep SS with sub-60 mV/dec was measured. Conversely, when the gate bias was swept forward from a negative voltage to a more positive value, these trapped electrons are released and transfer to the channel with the aid of a strong electric field. Therefore, the turn-on process of the device is also accelerated, and a deep SS is obtained. The above measured VGS sweep speed is about 4.8 μS/step. It was found that the SS values for the forward/reverse sweeps were still around 30 mV/dec when VDS = 10 V and a different VGS sweep rate of around 500 nS/step were adopted. This is due to the involvement of hot electrons depending on the electric field strength rather than the VGS sweep rate.SS can be expressed as SS = 2.3 m(kBT/q), where m is the body factor of the transistor and m = dVG/dΨa, kB is the Boltzmann constant, T is the temperature, and Ψa is the potential at the channel.33. Q. Xu, X. Liu, B. Wan, Z. Yang, F. Li, J. Lu, G. Hu, C. Pan, and Z. L. Wang, ACS Nano 12, 9608 (2018). https://doi.org/10.1021/acsnano.8b05604 Figures 2(e) and 2(f) show the schematics of the capacitor network of the conventional MISHEMT and the MISHEMT in this work, respectively. In the conventional MISHEMT, m is larger than 1; while in this work, it is smaller than 1 due to the intrinsic charge dynamic storage mechanism. As m can be expressed as m = 1 + (CGaN + Cit)/Cins, where CGaN, Cit, and Cin denote the capacitances due to the electron depletion in the channel, the capacitance due to the trapping effects, and the capacitance of the gate dielectric and barrier, respectively, the Cit here mathematically exhibits a negative value.The observed NDR in the IG [see Fig. 1(c)] is one of the evidence for the above proposed explanations on the mechanisms. As shown in Fig. 3(a), the NDR phenomenon in the IG can be explained as the reduction of the voltage drop cross the SiN because of the negative charge accumulation caused by the trapped electrons under the gate. This operation mechanism is similar to that of a typical floating-gate device.13,1413. Q. Han, T. C. U. Tromm, M. Hoffmann, P. Aleksa, U. Schroeder, J. Schubert, S. Mantl, and Q.-T. Zhao, IEEE Trans. Electron Devices 65, 4641 (2018). https://doi.org/10.1109/TED.2018.286372714. J.-S. Lee, Electron. Mater. Lett. 7, 175 (2011). https://doi.org/10.1007/s13391-011-0901-5 The operating voltages of the devices are much higher than the requirements in today's low power logic applications, more techniques need to be developed to further shrink the device dimensions.The AC-conductance method was used to evaluate the interface state density in the GaN MISHEMT. Figure 3(b) shows the time constant of the interface trap states as a function of bias voltage for the 75-nm gate device. Figure 3(c) presented the extracted interface trap density as a function of the trap energy for the 75-nm gate device. The extracted trap density is around 9.3 × 1012 cm−2 eV−1 at the energy around 0.382 eV and from 4.3 × 1012 to 5.9 × 1012 cm−2 eV−1 over the energy range from 0.398 to 0.406 eV. Table I lists the on/off current ratio (ION/IOFF), SS, and switching efficiency figure-of-merit (FOM) Q (defined as gmmax/SS,1515. W. Li, M. D. Brubaker, B. T. Spann, K. A. Bertness, and P. Fay, IEEE Electron Device Lett. 39, 184 (2018). https://doi.org/10.1109/LED.2017.2785785 gmmax is the transconductance peak of the device) for GaN HEMTs featuring sub-60 mV/dec SS reported in the literature. In this work, we demonstrated deep sub-60 mV/dec SS values independent of the gate bias sweep directions and a high value.

TABLE I. Comparison of the reported SS and switching efficiency FOM Q values in GaN HEMTs featuring sub-60 mV/dec SS in the literature.

AffiliationDevice structureVDD (V)ION/IOFFSS (mV/dec) (reverse/forward)gmmax (mS/mm)Q (μS dec/μm mV) (reverse/forward)HKUST66. Q. Zhou, S. Huang, H. Chen, C. Zhou, Z. Feng, S. Cai, and K. J. Chen, in 2011 International Electron Devices Meeting ( IEEE, Washington, D.C., 2011), pp. 33.4.1–33.4.4.Al2O3/InAlN/GaN101.0 × 10780/241121.4/4.6Intel77. H. W. Then, S. Dasgupta, M. Radosavljevic, L. Chow, B. Chu-Kung, G. Dewey, S. Gardner, X. Gao, J. Kavalieros, N. Mukherjee, M. Metz, M. Oliver, R. Pillarisetty, V. Rao, S. H. Sung, G. Yang, and R. Chau, in 2013 IEEE International Electron Devices Meeting ( IEEE, Washington, D.C., 2013), pp. 28.3.1–28.3.4.Al2O3/InAlN/GaN0.52.4 × 101095/40340.4/0.8UDEL88. P. Cui, G. Lin, J. Zhang, and Y. Zeng, IEEE Electron Device Lett. 41, 1185 (2020). https://doi.org/10.1109/LED.2020.3003337Oxide/InAlN/GaN101.7 × 10630/11844014.7/3.7This workIn situ SiN/AlGaN/GaN106.0 × 10829/2240013.8/18.2

In conclusion, we have experimentally demonstrated deep sub-60 mV/dec SS in in situ SiN/Al0.6Ga0.4N/GaN MISHEMTs on a Si substrate. Average SS values of 22 and 29 mV/dec were achieved at both forward and reverse VGS sweeps over 4 orders of ID range in a 75-nm gate device, respectively. The observed negative differential resistance (NDR) in the gate current and the capacitance spike in the depletion region of the C–V curves suggest that the capture and emission of the electrons in the traps are the dominant physical mechanisms responsible for the small SS.

This work was supported in part by the National Key R&D Program under Grant No. 2020YFB1807300, the Fundamental Research Project No. JCKY2020110B010, the Fundamental Research Funds for the Central Universities under Grant No. YJS2213, the Guangdong Key Area R&D Program under Grant No. 2020B010171002, and the National Science Fund for Distinguished Young Scholars under Grant No. 61925404.

Conflict of Interest

The authors have no conflicts to disclose.

Author Contributions

Hanghai Du: Investigation (equal); Writing – original draft (equal). JinCheng Zhang: Project administration (equal). Yue Hao: Supervision (equal). Zhihong Liu: Writing – review & editing (equal). Lu Hao: Data curation (equal). Guangjie Gao: Conceptualization (supporting). Weichuan Xing: Validation (equal). Weihang Zhang: Methodology (supporting). Yachao Zhang: Validation (equal). Hong Zhou: Formal analysis (supporting). Shenglei Zhao: Software (equal).

The data that support the findings of this study are available from the corresponding authors upon reasonable request.

REFERENCES

1. A. Rusu, G. A. Salvatore, D. Jiménez, and A. M. Ionescu, in 2010 International Electron Devices Meeting ( IEEE, 2010), pp. 16.3.1–16.3.4. Google Scholar2. A. Saeidi, T. Rosca, E. Memisevic, I. Stolichnov, M. Cavalieri, L.-E. Wernersson, and A. M. Ionescu, Nano Lett. 20, 3255 (2020). https://doi.org/10.1021/acs.nanolett.9b05356, Google ScholarCrossref3. Q. Xu, X. Liu, B. Wan, Z. Yang, F. Li, J. Lu, G. Hu, C. Pan, and Z. L. Wang, ACS Nano 12, 9608 (2018). https://doi.org/10.1021/acsnano.8b05604, Google ScholarCrossref4. K. S. Singh, S. Kumar, K. Nigam, and V. A. Tikkiwal, in 2019 International Conference on Signal Processing and Communication (ICSC) ( IEEE, 2019), pp. 286–291. Google ScholarCrossref5. D. Han, G. Bonomo, D. C. Ruiz, A. M. Arabhavi, O. J. S. Ostinelli, and C. R. Bolognesi, IEEE Trans. Electron Devices 69, 3549 (2022). https://doi.org/10.1109/TED.2022.3171736, Google ScholarCrossref6. Q. Zhou, S. Huang, H. Chen, C. Zhou, Z. Feng, S. Cai, and K. J. Chen, in 2011 International Electron Devices Meeting ( IEEE, Washington, D.C., 2011), pp. 33.4.1–33.4.4. Google Scholar7. H. W. Then, S. Dasgupta, M. Radosavljevic, L. Chow, B. Chu-Kung, G. Dewey, S. Gardner, X. Gao, J. Kavalieros, N. Mukherjee, M. Metz, M. Oliver, R. Pillarisetty, V. Rao, S. H. Sung, G. Yang, and R. Chau, in 2013 IEEE International Electron Devices Meeting ( IEEE, Washington, D.C., 2013), pp. 28.3.1–28.3.4. Google ScholarCrossref8. P. Cui, G. Lin, J. Zhang, and Y. Zeng, IEEE Electron Device Lett. 41, 1185 (2020). https://doi.org/10.1109/LED.2020.3003337, Google ScholarCrossref, ISI9. B. Song, M. Zhu, Z. Hu, M. Qi, X. Yan, Y. Cao, E. Kohn, D. Jena, and H. G. Xing, in 2014 Silicon Nanoelectronics Workshop (SNW) ( IEEE, Honolulu, HI, 2014), pp. 1–2. Google Scholar10. Q. Dai, D.-H. Son, Y.-J. Yoon, J.-G. Kim, X. Jin, I.-M. Kang, D.-H. Kim, Y. Xu, S. Cristoloveanu, and J.-H. Lee, IEEE Trans. Electron Devices 66, 1699 (2019). https://doi.org/10.1109/TED.2019.2900995, Google ScholarCrossref, ISI11. H. Du, Z. Liu, L. Hao, W. Xing, W. Zhang, H. Zhou, J. Zhang, and Y. Hao, Appl. Phys. Lett. 121, 172102 (2022). https://doi.org/10.1063/5.0100329, Google ScholarScitation12. M. Wang and K. J. Chen, IEEE Electron Device Lett. 32, 482 (2011). https://doi.org/10.1109/LED.2011.2105460, Google ScholarCrossref, ISI13. Q. Han, T. C. U. Tromm, M. Hoffmann, P. Aleksa, U. Schroeder, J. Schubert, S. Mantl, and Q.-T. Zhao, IEEE Trans. Electron Devices 65, 4641 (2018). https://doi.org/10.1109/TED.2018.2863727, Google ScholarCrossref14. J.-S. Lee, Electron. Mater. Lett. 7, 175 (2011). https://doi.org/10.1007/s13391-011-0901-5, Google ScholarCrossref15. W. Li, M. D. Brubaker, B. T. Spann, K. A. Bertness, and P. Fay, IEEE Electron Device Lett. 39, 184 (2018). https://doi.org/10.1109/LED.2017.2785785, Google ScholarCrossref© 2023 Author(s). Published under an exclusive license by AIP Publishing.