Digital coherent communication has been widely adopted in the fields of fiber networks and free-space communications due to its high sensitivity and robustness against transmission interference [1], [2]. Digital signal processing (DSP) algorithms are critical to digital coherent communication and are typically implemented in FPGAs or ASICs [3] to overcome various impairments and offer improved sensitivity. DSPs parallelization is necessary to process up to hundreds of giga sample/s real-time digital coherent communication [4] with a general hardware clock frequency of several hundred MHz [5]. Increasing the number of parallels can cost more hardware resources. Therefore, low-complexity DSPs become critical to real-time hardware systems. Typically, DSP flows for coherent receivers include IQ-imbalance compensation [6], clock recovery [7], adaptive equalization [8], frequency offset recovery [9], and carrier phase estimation [10]. Among these, adaptive equalization consists of finite impulse response (FIR) modules and tap coefficients update modules, which are responsible for a large part of the overall complexity [11], [12]. Therefore, reducing the complexity of adaptive equalizer is significant for realizing real-time hardware system.

To find a low-complexity solution, a series of simplified adaptive equalizer have been proposed [11], [12], [13], [14], [15], [16], [17], [18]. Among them, K. Matsuda et al. proposed a simplified AEQ by dividing the N-taps butterfly FIR filters into two sections (called KM-AEQ) [11]. The first section consists a 1-tap complex-valued 2×2 MIMO (Multiple-Input Multiple-Output) [8], which is used for polarization division demultiplexing, while the second stage consists of two complex-valued N-taps FIR filters that are employed for adaptive equalization. Therefore, compared with the conventional 2 × 2 MIMO, the number of taps in the FIR filter is halved. However, this simplified adaptive equalizer is sensitive to IQ impairment [12].

To solve the aforementioned points, we propose a low-complexity two-stage equalizer which can be used in real-time system. In the first-stage, we use 1-tap real-valued 4 × 4 MIMO [19] filters to compensate IQ impairment and polarization demultiplexing. In the second-stage, we use two N-taps real-valued FIR filters for equalization. We conducted a 112 Gbits/s PM-QPSK back-to-back (B2B) experiment with receiver IQ impairment emulation module to evaluate the performance of the proposed equalizer under different parallels. The experimental results demonstrate that, under 3 dB receiver IQ amplitude imbalance, the BER performance of the proposed equalizer is slightly better than that of the conventional 2×2 MIMO. Besides, under different receiver IQ phase/ amplitude imbalance, in serial case and 128-parallels case, compared with the conventional 2×2 MIMO and KM-AEQ are sensitive to IQ impairment, the proposed equalizer can compensate receiver IQ amplitude imbalance from 0 to 6 dB or receiver IQ phase imbalance from 0 to 30 degrees. Meanwhile, as for FIR module, compared with the conventional 2×2 MIMO and KM-AEQ, the number of multipliers can be respectively reduced by approximately 70% and 45% by use of 21 taps.