High–low Kelvin probe force spectroscopy for measuring the interface state density

To understand the principle of the high–low KPFS proposed in this study, we discuss the electrostatic forces acting between the tip and the sample when high- and low-frequency AC bias voltages are applied. The tip and the sample are assumed to be metallic and semiconducting, respectively, and a metal–insulator–semiconductor (MIS) structure consisting of the metallic tip, a vacuum gap, and the semiconducting sample is considered (Figure 1a). No oxide film on the semiconductor surface is assumed, and to simplify the discussion, the CPD between the tip and the semiconductor substrate is assumed to be zero.

[2190-4286-14-18-1]

Figure 1: (a) Schematic of the metal tip–gap–semiconductor sample. (b) Energy band diagram of the metal–gap–semiconductor sample. Emission and capture of carriers (electrons and holes) occur between the interface and bulk states of the semiconductor sample when a low-frequency AC bias voltage is applied.

To investigate the electrostatic force acting between the tip and the semiconductor surface, we use the theoretical model reported by Hudlet and co-workers [23]. For simplicity, let us assume that the tip and the sample are represented by parallel plate capacitors. In this case, the electrostatic force Fele acting between the tip and the semiconductor surface is expressed as

[2190-4286-14-18-i1](1)

where Q is the charge per unit surface area induced on the semiconductor surface and ε0 is the dielectric constant of vacuum.

A bias voltage Vdc + Vac·cos 2πft is applied between the tip and the semiconductor sample, where Vdc, Vac, and f are the DC bias voltage, amplitude of the AC bias voltage, and modulation frequency of the AC bias voltage, respectively. The modulated electrostatic force Fele(f) between the tip and the surface is expressed as follows using Taylor series expansion:

[2190-4286-14-18-i2](2)

where Vs is the surface potential of the semiconductor sample.

Next, we consider the charge Q induced on the semiconductor surface. When a bias voltage is applied between a metal tip and a semiconductor surface, a surface potential is generated on the semiconductor surface, resulting in, for example, surface charge accumulation, depletion, and inversion states. The relationship between this surface charge and the electrostatic force between the tip and the sample has already been discussed by Hudlet and co-workers [23]. Additionally, there are interface states on the semiconductor surface. Therefore, the contribution of these interface states to the AC component of the electrostatic force must be considered. When an AC bias voltage is applied between the tip and the sample, the bulk Fermi level does not change on the semiconductor side, whereas the interface states move up and down with the conduction and valence bands. This causes capture of carriers (electrons and/or holes) from the bulk side by the interface states and, conversely, emission of carriers from the interface states to the bulk side, which contribute to the electrostatic force (Figure 1b). Therefore, the total charge Q induced on the semiconductor surface by the voltage application is given by the sum of the charge Qs due to the surface potential Vs and the charge Qit due to the interface states as follows:

[2190-4286-14-18-i3](3)

Here, we consider the charge Qs due to the surface potential Vs. In the case of an n-type semiconductor, the charge Qs as a function of the surface potential Vs is expressed as follows [23,24]:

[2190-4286-14-18-i4](4) [2190-4286-14-18-i5](5) [2190-4286-14-18-i6](6) [2190-4286-14-18-i7](7)

where ND is the dopant density, ni is the intrinsic carrier density, and ε is the dielectric constant. LD is the Debye length for majority carriers (electrons), which characterizes the change in the potential inside the semiconductor. kB, T and e are the Boltzmann constant, absolute temperature, and elementary charge (e > 0), respectively.

Since the applied voltage V is divided between the semiconductor and the gap, the following equation is obtained:

[2190-4286-14-18-i8](8)

where Cg is the capacitance per unit surface area due to the gap between the tip and the surface. The charge Qs due to the surface potential Vs is obtained by numerically solving Equations 4–8.

When a positive or negative bias voltage is applied to the MIS structure consisting of the metal tip, gap, and semiconductor sample, three cases exist at the semiconductor surface. For an n-type semiconductor, when a positive bias voltage is applied to the metal tip (Vdc > 0), electrons (majority carriers) in the semiconductor are attracted to the surface, forming an accumulation layer of electrons. When a small negative bias voltage is applied to the metal tip (Vdc < 0), electrons (majority carriers) in the semiconductor are depleted from the surface, forming a depletion layer. When a large negative bias voltage is applied to the metal tip, the number of holes (minority carriers) is greater than that of electrons at the surface, and holes are induced in the semiconductor at the surface, forming an inversion layer of holes.

Here, in the accumulation region, since [Graphic 1] and exp(u) ≫ |u + 1|, Qs is dominated by the first term in Equation 5 and is given by [23,24]

[2190-4286-14-18-i9](9)

In the depletion region, Qs is dominated by the second term −u in the square brackets on the right-hand side of Equation 5 and is given by

[2190-4286-14-18-i10](10)

In the strong inversion region, Qs is dominated by the fourth term [Graphic 2] in the square brackets on the right-hand side of Equation 5 and is given by

[2190-4286-14-18-i11](11)

Similar results can be obtained for a p-type semiconductor.

Next, we consider the charge Qit due to the interface states. In indirect-bandgap semiconductors such as Si with a low carrier density below 1017 cm−3, the charge (electron and hole) transfer between the interface and bulk states at low carrier density can be explained by the model with Shockley–Read–Hall (SRH) statistics [25,26]. This model is based on the charge capture and emission between the interface and bulk states (Figure 2). Assume that [Graphic 3] and [Graphic 4] are the capture rates for electrons and holes per electron and hole, respectively, when all interface states are unoccupied, and [Graphic 5] and [Graphic 6] are the emission rates for electrons and holes per electron and hole, respectively. The capture rates per unit volume for electrons and holes ([Graphic 7] and [Graphic 8]) are given by [25,26]

[2190-4286-14-18-i12](12) [2190-4286-14-18-i13](13)

where fit is the fraction of occupied interface states. n and p are the electron and hole densities of the bulk state. Analogously, the emission rates per unit volume for electrons and holes ([Graphic 9] and [Graphic 10]) are given by

[2190-4286-14-18-i14](14) [2190-4286-14-18-i15](15)

In thermal equilibrium, the amount of capture and the amount of emission for a carrier coincide as follows:

[2190-4286-14-18-i16](16) [2190-4286-14-18-2]

Figure 2: Schematic model of carrier emission and capture between the interface and bulk states of the semiconductor sample.

The net generation/recombination rate RSRH is given by the following equation [25,26]:

[2190-4286-14-18-i17](17)

with

[2190-4286-14-18-i18](18) [2190-4286-14-18-i19](19)

The index 0 indicates equilibrium quantities. For low-level injection, at which the excess minority carrier density is low compared to the equilibrium majority carrier density, the net generation/recombination rate RSRH is dominated by the hole (minority carrier) lifetime τp in n-type semiconductors and the electron (minority carrier) lifetime τn in p-type semiconductors as follows:

[2190-4286-14-18-i20](20) [2190-4286-14-18-i21](21)

where σn and σp are the capture cross sections for electrons and holes, respectively, vth is the thermal velocity, and Nit is the concentration of interface states. These equations indicate that the carrier lifetimes τp and τn are reciprocals of the capture rates per single carrier determined by the capture cross sections σn and σp, thermal velocity vth, and concentration of interface states Nit, which depend on semiconductor type, temperature, carrier density, and interface state density.

For an n-type Si semiconductor at room temperature, the hole (minority carrier) lifetime τp as a function of electron (majority carrier) density n has been experimentally investigated and is reported to be less than 2.5 × 10−5 s for low carrier densities n < 5 × 1017 cm−3[26]. Additionally, for metal-oxide semiconductor capacitors on Si(100) substrates, the lifetimes τn and τp as functions of the sum of the surface potential and the Fermi potential with respect to the midgap have been experimentally investigated [24]. As a result, for Si semiconductors with a low carrier density (small Fermi potential), the lifetime has been reported to be less than 5 × 10−6 s. These results indicate that the cutoff frequency fc of carrier transport between the interface and bulk states for a Si substrate with a low carrier density is approximately 200 kHz. Therefore, when an AC bias voltage with a frequency higher than this cutoff frequency fc is applied between the tip and the Si semiconductor sample, the charge Qit caused by the interface states cannot respond to changes in the surface potential. In contrast, when an AC bias voltage with a frequency much lower than fc is applied between the tip and the Si semiconductor sample, the charge Qit can respond to changes in the surface potential.

Low KPFS

First, we consider the case in which the frequency of the AC bias voltage is lower than the cutoff frequency fc of the carrier transport between the interface and bulk states. The AC bias voltage Vac·cos 2πfmt is applied between the tip and the surface, where fm is the modulation frequency of the AC bias voltage. Since the charge Qit due to interface states can follow the change in the surface potential, dQ/dVs and dVs/dV can be expressed as

[2190-4286-14-18-i22](22) [2190-4286-14-18-i23](23)

where CD and Cit are the capacitance per unit surface area due to the depletion layer of the semiconductor and the capacitance due to the interface charge, respectively. The applied voltage is divided between the semiconductor and the gap, and the following equation is obtained:

[2190-4286-14-18-i24](24)

Therefore, the modulation frequency fm component of the electrostatic force Fele(fm) acting on the probe is expressed as

[2190-4286-14-18-i25](25) [2190-4286-14-18-i26](26)

where CLF is the low-frequency tip–sample capacitance. The equivalent circuit for this capacitance CLF is shown in Figure 3b. Note that this equivalent circuit is equal to the equivalent circuit of the impedance model (SRH model) of the MIS structure (Figure 3a), neglecting the resistance component Rit. This result suggests a similarity between conventional impedance measurements and electrostatic force measurements in semiconductor surface and interface evaluation techniques.

[2190-4286-14-18-3]

Figure 3: (a) Equivalent circuit of the impedance model (SRH model) of the MIS structure. (b) Equivalent circuit of tip–sample capacitance CLF in low-frequency KPFS with a low-frequency AC bias voltage. (c) Equivalent circuit of tip–sample capacitance CHF in high-frequency KPFS with a high-frequency AC bias voltage. Cg: capacitance due to the tip–surface gap; CD: capacitance due to the depletion layer; Cit: capacitance due to interface states; Rit: resistance due to interface states.

The average distance between the tip and the sample is zto, and the amplitude and frequency of the vibrating cantilever are A and f0, respectively. The time-varying tip–sample distance is given by

[2190-4286-14-18-i27](27)

From this equation and the relationship Cg = ε0/z, we obtain the following expression:

[2190-4286-14-18-i28](28)

Because of frequency mixing between the electrostatic force due to the AC bias voltage cos 2πfmt and the cantilever vibration cos 2πf0t, f0 ± fm components of the electrostatic force Fele,L(f0 ± fm) appear:

[2190-4286-14-18-i29](29)

When the electrostatic force is detected by the FM method, the electrostatic force Fele,L(f0 ± fm) is demodulated into the fm component of the frequency shift ΔfL(fm), which is expressed as

[2190-4286-14-18-i30](30)

where k is the spring constant of the cantilever. This equation indicates that the slope of the dependence of the fm component of the frequency shift ΔfL(fm) on the DC bias voltage Vdc (ΔfL(fm)–Vdc curve) is proportional to the capacitance inside the semiconductor at a low-frequency AC bias (CD + Cit).

High KPFS

Next, we consider the case in which the frequency of the AC bias voltage is higher than the cutoff frequency fc of the carrier transport between the interface and bulk states. We assume that the heterodyne FM method [21] is used and that an AC bias voltage with a high frequency near twice the vibration frequency of the cantilever Vac·cos 2π(2f0 + fm)t is applied (that is, f = 2f0 + fm). In the high-frequency case, the contribution from the interface charge Qit due to interface states cannot follow the change in surface potential Vs, so this contribution can be neglected. Therefore, dQ/dVs and dVs/ dV can be expressed as

[2190-4286-14-18-i31](31) [2190-4286-14-18-i32](32)

Since the applied voltage is divided between the semiconductor and the gap, the following equation is obtained:

[2190-4286-14-18-i33](33)

Therefore, the modulation frequency (2f0 + fm) component of the electrostatic force Fele(2f0 + fm) acting on the tip is expressed as

[2190-4286-14-18-i34](34) [2190-4286-14-18-i35](35)

where CHF is the high-frequency tip–sample capacitance. The equivalent circuit for this capacitance CHF is shown in Figure 3c. Note that this equivalent circuit is equal to the equivalent circuit of the impedance of the MIS structure derived from the SRH model (Figure 3a), neglecting the capacitance component Cit and resistance component Rit due to the semiconductor interface states.

Now, the capacitance CD of the depletion layer of the MIS structure is given by CD = |dQs/dVs|. In the charge accumulation region, from Equation 9, CD is given by

[2190-4286-14-18-i36](36)

In the depletion region, from Equation 10, CD is given by

[2190-4286-14-18-i37](37)

In the inversion region, from Equation 11, CD is given by

[2190-4286-14-18-i38](38)

Therefore, in the depletion region, we can obtain the following expression:

[2190-4286-14-18-i39](39)

In the accumulation and inversion regions, we can obtain the following expression:

[2190-4286-14-18-i40](40)

Because of frequency mixing between the electrostatic force due to the AC bias voltage cos 2π(2f0 + fm)t and the cantilever vibration cos2πf0t, the f0 + fm component of the electrostatic force Fele,H(f0 + fm) appears:

[2190-4286-14-18-i41](41) In the accumulation and inversion regions, [2190-4286-14-18-i42](42)

In the FM method, the electrostatic force Fele,H(f0 + fm) is demodulated into the fm component of the frequency shift ΔfH(fm). The resulting fm component of the frequency shift ΔfH(fm) is expressed in the depletion region as

[2190-4286-14-18-i43](43)

and in the accumulation and inversion regions as

[2190-4286-14-18-i44](44)

In the above equations, the slope of the dependence of the fm component of the frequency shift ΔfH(fm) on Vdc (ΔfH(fm)–Vdc curve) is proportional to the capacitance CD inside the semiconductor in the depletion region and to the gap capacitance Cg in the accumulation and inversion regions. Note that at a high-frequency AC bias voltage, as shown in Equation 43 and Equation 44, only the f0 + fm component of the electrostatic force Fele,H(f0 + fm) is demodulated, while at a low-frequency AC bias voltage, as shown in Equation 30, the f0 + fm and f0 − fm components of the electrostatic force Fele,L(f0 ± fm) are demodulated. Therefore, the coefficients in Equation 43 and Equation 44 are 1/2 of those in Equation 30.

High–low KPFM

Here, we consider the derivation of the surface potential Vs induced by the interface states. When the KPFM measurement is performed using a low-frequency AC bias voltage, the DC bias voltage that makes the modulation component of the frequency shift ΔfL(fm) zero is

[2190-4286-14-18-i45](45)

Here, Vs(LF) can be thought of as reflecting information about the sum of the surface potential (band bending) due to the interface states and the CPD between the metal tip and the bulk state of the sample. This is because when a low-frequency AC bias voltage is used, the charge Qit can respond to changes in the surface potential. In contrast, when the KPFM measurement is performed using a high-frequency AC bias voltage, the DC bias voltage that makes the modulation component of the frequency shift ΔfH(fm) zero is

[2190-4286-14-18-i46](46)

Here, Vs(HF) can be thought of as reflecting information about the CPD between the metal tip and the bulk state of the sample. This is because when a high-frequency AC bias voltage is used, the charge Qit caused by the interface states cannot respond to changes in the surface potential. Therefore, as shown in the next equation, high–low KPFM, which measures the difference between Vs(LF) with a low-frequency AC bias voltage and Vs(HF) with a high-frequency AC bias voltage, reflects the information of the surface potential (band bending) due to the interface states [21,22].

[2190-4286-14-18-i47](47)

Regarding the selection of ±, + is for applying a bias voltage to the sample and − is for applying a bias voltage to the tip. The + and − signs of ΔVs indicate upward and downward band bending at the interface, respectively.

High–low KPFS

Next, let us consider the derivation of the interface state density Dit from Equation 30 and Equation 43, which relate the modulation components of the frequency shift to the AC bias voltage at low and high frequencies. In the case of a low-frequency AC bias, from Equation 30, the slope of the ΔfL(fm)–Vdc curve is proportional to the low-frequency capacitance inside the semiconductor (CD + Cit). In the case of a high-frequency AC bias, from Equation 43, twice the slope of the ΔfH(fm)–Vdc curve in the depletion region is proportional to the high-frequency capacitance within the semiconductor (CD ). Using these relationships, the interface state density Dit at each DC bias voltage Vdc can be obtained by taking the difference in the slope of the dependence of Δf(fm) on the DC bias voltage for low and high frequencies (the capacitance Cit due to the interface charge) [24] as follows:

[2190-4286-14-18-i48](48) Δf–Vdc curve with low- and high-frequency AC bias voltages

We consider the derivation of the Δf–Vdc curve. The DC electrostatic force Fele(0) between the tip and the surface when using an AC bias voltage with frequency f (= fm or 2f0 + fm) is expressed as follows using Taylor series expansion up to the second-order terms:

[2190-4286-14-18-i49](49)

The contribution of the second-order terms of the Taylor series expansion of the electrostatic force is much smaller than that of the zeroth-order term and can be ignored. Qs can be obtained by solving Equations 4–8 numerically, but the relationship between the DC bias voltage Vdc and the frequency shift Δf cannot be understood analytically.

Therefore, assuming that the vibration amplitude of the cantilever is very small compared to the length of the electrostatic force interaction region, we can obtain the analytical relationship between Vdc and the frequency shift Δf. The gradient of the electrostatic force is given by

[2190-4286-14-18-i50](50)

From Equations 24 and 33 and the relationship Cg = ε0/z, dVs/dz is given by

[2190-4286-14-18-i51](51)

and

[2190-4286-14-18-i52](52)

for low- and high-frequency AC bias voltages, respectively. From Equations 22, 24, 31, and 33, the frequency shift of the electrostatic force is given by

[2190-4286-14-18-i53](53)

and

[2190-4286-14-18-i54](54)

for low- and high-frequency AC bias voltages, respectively. As shown in Equations 36–38, CD in the charge depletion region is very different from CD in the charge accumulation and charge inversion regions. Thus, these equations suggest that the ΔfL–Vdc curve for a low-frequency AC bias voltage is almost parabolic with respect to Vdc when CD < Cit, while the ΔfH–Vdc curve for a high-frequency AC bias voltage is divided into three regions with respect to Vdc. These analytical equations do not necessarily quantitatively agree with the experimental results because they approximate small cantilever vibration amplitudes, but they can qualitatively explain the behavior of Δf–Vdc curves.

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